MATLABÂ® and SimulinkÂ® for Model-Based Design provide signal, image, and video processing engineers with a development platform that spans design, modeling, simulation, code generation, and implementation. Engineers who use Model-Based Design to target FPGAs or ASICs can design and simulate systems with MATLAB, Simulink, and StateflowÂ® and then generate bit-true, cycle-accurate, synthesizable VerilogÂ® and VHDL code using HDL Coderâ„¢. Alternatively, engineers who specifically target Xilinx FPGAs can use a XilinxÂ® library of bit- and cycle-true blocks to build a model in Simulink. They can then use Xilinx System Generator for DSPâ„¢, a plug-in to Simulink code generation software, to automatically generate synthesizable hardware description language (HDL) code mapped to pre-optimized Xilinx algorithms.
Xilinx System Generator (XSG) is an integrated design environment (IDE) for FPGAs, which uses Simulink, as a development environment and is presented in the form of blockset. It has an integrated design flow, to move directly to the configuration file (*. bit) necessary for programming the FPGA.
One of the most important features of Xilinx System Generator is possessed abstraction arithmetic, that is working with representation in fixed point with a precision arbitrary, including quantization and overflow. You can also perform simulations both as a fixed point double precision. XSG automatically generates VHDL code and a draft of the ISE model being developed. Make hierarchical VHDL synthesis, expansion and mapping hardware, in addition to generating a user constraint file (UCF), simulation and testbech and test vectors among other things. Xilinx System Generator was created primarily to deal with complex Digital Signal Processing (DSP) applications , but it has other applications like the theme of this work.
The blocks in Xilinx System Generator operate with Boolean values or arbitrary values in fixed point, for a better approach to hardware implementation. In constrast Simulink works with numbers of double-precision floating point. The connection between blocks Xilinx System Generator and Simulink blocks are the gateway blocks
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